1. Field of the Invention
The present invention relates to a microprocessor, and more particularly to a bus interface used for making an external access to a memory integrated in the microprocessor and for filling a cache integrated in the microprocessor with instructions/data.
2. Description of the Background Art
A microprocessor with an integrated memory has been well known in the background art. FIG. 27 is a block diagram showing a configuration of the microprocessor with an integrated RAM, for example. A microprocessor 201 includes a CPU 1, an integrated RAM 29, a bus 59 and a bus interface unit (BIU) 39. The integrated RAM 29 may be a program RAM (including a ROM) or may be a data RAM (including a ROM). An SRAM has been used as the integrated RAM 29 to allow an access by one clock. A memory region of the integrated RAM 29 is specified by an address and accessed with an instruction.
In some cases, outside the microprocessor 201, an external memory 4 is provided and connected thereto through a bus 60. For example, a DRAM is used as the external memory 4. To control it, in some cases, the microprocessor 201 integrates a DRAM controller, a DMA controller (DMAC) and the like.
FIG. 28 is a block diagram showing a configuration of a microprocessor with an integrated cache memory (simply referred to as "cache" hereinafter). A microprocessor 202 includes the CPU 1, a cache 28, the bus 59 and BIU 39. Outside the microprocessor 202, the external memory 4 is provided and connected thereto through the bus 60. The cache 28 makes a caching of instructions and data stored in the external memory 4 and to be used in the microprocessor 202.
As a matter of course, both the RAM 29 and the cache 28 may be integrated in a microprocessor and the integrated cache 28 may make a caching of instructions and data stored in the integrated memory 29. However, the integrated memory 29 does not need a caching since it is a ROM or SRAM and can be accessed by about one clock.
The SRAM requires more area per cell than the DRAM, and accordingly it is impossible to achieve high-integration of SRAM. For this reason, a microprocessor is required to integrate a CPU core and the DRAM on one chip for high integration of memory. However, the DRAM has a disadvantage of slow access, and the time for memory access causes degradation in performance of a CPU.
If an external bus master (control means for accessing a memory through a bus) is provided besides the CPU integrated in the microprocessor, separate transfers of signals between the respective bus masters and the memory causes an increase in the required number of pins in the microprocessor.